COMP  273    (Winter 2016)
Introduction to Computer Systems

Mon/Wed  2:35-3:55 pm     ENGMC 304

INSTRUCTOR

  Professor   Michael Langer

  office hours:   Mon/Wed  4:00-5:00 pm     ENGMC 329
TEACHING ASSISTANTS
    Unless otherwise specified, TAs will hold office hours in the following locations:

    Ben (ENGMC 224), Hasan (ENGMC 312), Noor (ENGTR 3090), Josh (ENGMC 112)
ANNOUNCEMENTS
  • The supplemental exam will be held on Aug 17, 2016. It covers the whole course, namely lectures 0 to 22. It will be short answer (not multiple choice). The grade will replace the final exam grade. It can also replace the quiz grades (same policy as final exam in April).
RESOURCES
LECTURE SCHEDULE + NOTES

Number representations
  1. Course introduction, binary numbers   (notes)   (slides)   (3x3)
  2. twos complement, float, hexadecimal (notes)   (slides)   (3x3)
  3. IEEE floating point (notes)   (slides)   (3x3)
Combinational logic
  1. [Quiz 1] truth tables, gates, multiplexor (notes)   (slides)   (3x3)
  2. ROM, arithmetic circuits, encoders, decoders, ALU (notes)   (slides)   (3x3)
Sequential logic
  1. RS latch, the clock, D latch, D flip flop  (notes)   (slides)   (3x3)
  2. registers, counters and timers, memory (notes)   (slides)   (3x3)
  3. multiplication, division, floating point ops (notes)   (slides)   (3x3)
MIPS Assembly Language
  1. instruction formats and examples 1 (notes)   (slides)   (3x3)
  2. [Quiz 2] instruction examples 2 (notes)   (slides)   (3x3)
  3. strings, arrays,  assembler directives, system calls (notes)   (slides)   (3x3)
  4. functions (notes)   (slides)   (3x3)   (sumton code)
  5. co-processors 0, 1 (notes)   (slides)   (3x3)
MIPS CPU Datapath and Control

The data path slides did not reduce to 3x3 properly so I have removed the links.
  1. [Quiz 3] single cycle model 1 (notes)   (slides)  
  2. single cycle model 2 (notes)   (slides)  
  3. STUDY BREAK
  4. multicycle model:   pipelining (notes)   (slides)  
Memory and I/O   
  1. physical vs. virtual memory, page tables (notes)   (slides)   (3x3)
  2. [Quiz 4] page table cache (TLB) (notes)   (slides)  
  3. data and instruction caches, hit and miss (notes)   (slides)  
  4. [Quiz 5] system bus, I/0 devices (notes)   (slides)   (3x3)
  5. memory mapped I/O, polling,  DMA   (notes)   (slides)   (3x3)
    EASTER WEEKEND
  6. interrupts     (notes)   (slides)   (3x3)
  7. asynchronous I/0       (notes)   (slides)   (3x3)
Special Topics (not on final exam)
  1. thinking of graduate school? (slides)
  2. [Quiz 6] A4 Q3 + associative caches (how caches work) (slides)  
  3. Java Virtual Machine (slides)
EXERCISES, EXAMS, ASSIGNMENTS, etc



Exercises 1

Quiz 1 with solutions



Exercises 2


Quiz 2 with solutions

Exercises 3


Assignment 1 (PDF) &   (starter code)   grading scheme
Assignment 2 (PDF) &   (starter and solution code)

Quiz 3 with solution

Exercises 4





Exercises 5

Quiz 4 with solutions  


Exercises 6

Quiz 5 with solutions  


Exercises 7

Assignment 3 (PDF)   (starter code)   (solution)   (grading)   (test code)

Quiz 6 with  

Assignment 4 (PDF)   (starter code)   (solution and grading)

Practice questions for final exam. (PDF)