The availability of small, low-power, low-cost FPGA’s make them appealing for the implementation of reconfigurable digital filters in audio signal processing applications. A Digital Signal Processing (DSP) unit with a Multiply-Accumulate (MAC) core can be used to implement digital filters where the arithmetic operations required occur sequentially. The speed and limited resources of low-cost FPGA’s limit the number of operations available to implement the digital filter. This thesis presents a reconfigurable digital filter compiler used to generate con- figuration data for a reconfigurable DSP unit used to implement a digital filter. The filter compiler automatically generates filter configurations that reduce the number of required operations to implement the digital filter. The finite-precision effects of the selected filter configuration on the magnitude frequency response are presented, allowing the user to choose an acceptable configuration.