A runtime reconfigurable Digital Signal Processing (DSP) unit using one’s complement data and a Minimum Signed Digit (MSD) multiplier is described. The MSD multiplier changes the partial product shift-and-add operations to shift-and-add/subtract operations and reduces the number of partial product terms by half, decreasing the size and increasing the speed of the multiplier. Using a carry-save architecture, the propagation delay of an adder to add the carry-out bits is eliminated. Taking advantage of the deterministic nature of the desired DSP algorithm, the runtime reconfiguration of the multiplier can be pipelined to eliminate an added set-up state. The described DSP unit compared to a DSP unit using a conventional multiplier is shown to be 20% faster and 30% smaller for a 32-bit coefficient and using Xilinx Field Programmable Gate Arrays (FPGAs) with 6-input Look-Up Tables (LUTs).