Assignment #2: Harmonic Frequency Synthesizer and FSK Modulator

due: February 13 by 9:30

This assignment may be done in pairs. You may use any VHDL simulation software with which you are familiar, such as Quartus II or Modelsim. Full specifications are available here.

Academic Integrity

The following is offered with apologies to the vast majority of students who do their work honestly and take their university learning seriously:

Your instructor takes academic integrity seriously and has no tolerance for plagiarism or any other form of academic misconduct. Failure to respect these guidelines will result in you receiving a grade of zero on this assignment.

Acceptable collaboration between students and teams might include:

discussing some aspect of the assignment specifications in attempting to understand a particular point
discussing operation of the Altera timing analysis tools
discussing a problem you encountered while implementing the ripple-carry adder

Sharing of any computer code between students, or re-using any code from a third party (e.g., open source) is acceptable, provided that you indicate this explicitly at the start of your report and (as comments) in the VHDL code. In this case, only the portion of work that you did individually will be considered toward your grade.

Unacceptable collaboration and violations of academic integrity include, but are not limited to:

including any code that was not your own and failing to indicate so
sharing part or all of your report with other students/teams (other than your partner)

If you are uncertain about any of these guidelines, please discuss with your instructor as soon as possible.

Specifications and Resources

The assignment specifications were provided originally by Ian Brynjolfson, a former TA for the lab.

Assignment specifications
Getting Started with the TimeQuest Timing Analyzer video tutorial
TimeQuest Example: Basic SDC Example

Grading scheme

Component	Evaluation rubric
Exercise 1: Implementation of ripple-carry adder and 5-bit register	0: not provided 3: implementation incomplete or poorly documented 5: implementation appears to be complete and reasonably documented
Exercise 1: Frequency synthesizer implementation	0: not provided 3: implementation incomplete or poorly documented 5: implementation appears to be complete and reasonably documented
Exercise 1: Simulation results	0: no waveforms provided 5: simulation results do not show all 5 frequency outputs 10: all 5 frequencies demonstrated as outputs but results poorly annotated 15: all requested frequencies demonstrated and clearly annotated
Exercise 1: maximum operational frequency reported from timing analysis	0: not provided or not plausible 5: results provided but not clear or otherwise obviously incorrect 10: results are reasonable and clearly shown
Exercise 2: pipelined version of ripple-carry adder with register	0: not provided 3: implementation incomplete or poorly documented 5: implementation appears to be complete and reasonably documented
Exercise 2: Simulation results	0: no waveforms provided 5: simulation results do not show all 5 frequency outputs 10: all 5 frequencies demonstrated as outputs but results poorly annotated 15: all requested frequencies demonstrated and clearly annotated
Exercise 2: maximum operational frequency reported from timing analysis	0: not provided or not plausible 5: results provided but not clear or otherwise obviously incorrect 10: results are reasonable and clearly shown
Exercise 3: Demonstration of FSK Modulator	0: results not provided 10: results demonstrate switching between 10 and 11 MHz waveforms but lacking adequate annotation and/or failing to satisfy other requirements 20: clearly annotated results demonstrating switching between 10 and 11 MHz waveforms with either 50-50 duty cycle or no phase discontinuity between frequency transitions 30: clearly annotated results demonstrating both switching between 10 and 11 MHz waveforms with 50-50 duty cycle and no phase discontinuity at frequency transitions
Exercise 4 (bonus): Analog waveform generator	0: not implemented 10: VHDL appears to have "gotten close" to a working implementation, but does not output (approximate) sine waves 15: VHDL achieves output of sine wave at least for one frequency 20: VHDL is clearly annotated and output demonstrates sine wave outputs at multiple frequencies
Presentation	0: presentation offered no understanding of group's accomplishments on the assignment 3: some important content was provided but presentation was generally not well organized or timed 7: reasonably timed and understandable delivery, content was generally clear and provided general sense of the group's accomplishments on the assignment, even if incomplete 10: well timed and understandable delivery, content was clearly presented and organized, slides contained appropriate selection of most relevant material, covering the results of Exercises 1-3 (bonus optional)