Basic software tools used in the design, synthesis and analysis of
computer and communication sytems such as data-paths, switching
circuits, and arithmetic and logic circuits. Behavioral and structural
modeling of hardware designs in the IEEE standard hardware designs using
Programmable Logic Devices.
Learning outcomes
Expectations and focus
Textbook
Evaluation
Late work policy
Academic integrity
You will gain familiarity with VHDL simulation and analysis tools through two assignments and further experience with specification, simulation, synthesis, and test benching of a larger system through the project.
Your marks will be based on two assignments and a group project.
The term project will be done in groups -- ideally
two-to-three students per group. Each member must take on a primary
responsibility of at least one component and identify his or her role.
While team members may work together on multiple aspects of the
project and are encouraged to do so, specific responsibilities of each
member must be delineated.
All assigned work is due at 9:30 on the listed date and must be
submitted on-line through
moodle.
In cases of illness
or other compelling reason warranting an extension, the student(s)
must notify the instructor at least one week in advance of the due
date, in order to make special arrangements. Barring such advance
notice,
no credit will be given for late work.
Your instructor values it. Google my name with "academic integrity".
Last updated on 16 February 2017