ECSE 222: Digital Logic

ECSE 222: Digital Logic
Fall 2017 — McGill UniversityElectical & Computer Engineering
Prof. Derek Nowrouzezahrai
contents

1  Requirements
2  Readings
  2.1  Assignments & Labs
  2.2  Late Policy & Extensions
3  Evaluation
4  Lecture Schedule & Content
5  Ethics

Logic gates by SparkFun
Every digital hardware device you've encountered, regardless of its complexity, is built by combining a small set of very simple logical building blocks. This course will familiarize you with these logic gates, as well as how they are combined into logic circuits capable of performing computational tasks.

We will first introduce you to the theory of boolean algebra and how it relates (directly) to the operation of digital logic circuits, before exposing you to the various ways one goes about designing digital circuits. We will discuss the importance of optimizing circuits, all while building a set of algebraic tools necessary to perform various optimizations.

This course also has a complementary technical lab component, where you'll get to put many of the theoretical concepts we discuss in class to use on real-world problems: designing circuits that "do things". No abstract or pedantic applications; you'll get to work on the types of problems that an entry-level hardware designer would be expected to do in the Real WorldTM.

This syllabus may be revised during the semester. The latest version is always online at http://www.cim.mcgill.ca/~derek/ecse222.html

For all administrative/registration issues, please do not contact the course staff: instead, contact the McGill ECE Undergraduate Programs Administrator. I will not reply to any e-mails pertaining to administrative issues or to information provided during lectures.

Requirements

Prerequisites

Textbook (on reserve at the library and available at the McGill Bookstore)

  • Brown and Vranesic, Digital Logic with VHDL Design, 3rd Ed, McGraw-Hill.

Equipment

Altera DE1-SoC: 222's official hammer.

Each lab team will be responsible for signing out (and returning, on time!) an Altera DE1-SoC FPGA board for use when developing and testing your lab assignments. You will be able to do some of the design and simulation work outside of the actual lab sessions, using software that you can install on your own laptops/desktops. During the 2-hour lab sessions, lab time will be used to demonstrate your lab experiments to the TAs for evaluation.

Time

Putting pen to paper: do this FTW.
I strongly recommend attending lectures: you'll save more time (and hopefully gain a better understanding) following the instructor face-to-face through the course slides, compared to exclusively and independently reading the slides (and/or the textbook).

Plan to invest an average of 2 to 4 hours per week on this course, in addition to the (almost) 3 hours of lecture and 2 hours of tutorials/labs. The balance will shift from (possibly) fewer hours spent on pen-and-paper assignments early in the semester, to (possibly) longer hours spent working on the labs later in the semester.

It's a good idea to get in the habit of spending the time necessary to understand the course topics, in part through an independent completion of the pen-and-paper assignments, early on in the semester. In the latter-half of the course, when labs begin, the pace of the course will accelerate significantly. Here, it's essential that you communicate effectively with your lab partner: I recommend a “work to understand stuff together” approach, rather than a “divide-and-conquer” approach, for the labs.

All that being said, it's should be clear that you have complete freedom in how you choose to spend your time: there may very well be many valid paths to success in ECSE 222, and the ones I outlined above are motivated simply by the habits I've observed from successful students over the years.

Participation

Don't be shy: speak up in class.
ECSE 222 is a mandatory course in the ECSE curriculum, which means we're going to have large classes. I love teaching to large classes, and I'm going to call on you to help foster a genuine environment of investigation during the semester. Many of the lectures will include example problems that we'll solve together in class. The operative word here, “together”, means that I'm not just going to walk you through solutions... it means that we're going to stumble through solutions together, through discussion.

Now's not the time to be shy! When in class: ask questions, take risks (you're not being graded on what you say in class!), don't be afraid to give a wrong answer... often, it's the wrong answers that spark the most interesting discussions.

Readings

My course slides and lectures will be based very closely on the textbook for the course, Brown and Vranesic's Digital Logic with VHDL Design (3rd edition, McGraw-Hill). The course schedule below makes reference to relevant textbook sections for each lecture, however, if you pay attention and participate during class, the textbook readings can serve primarily as supplemental instruction: it's always handy to hear someone different (in this case, Brown and Vranesic) explain the same ideas that I will cover in the class, but there won't be additional information of relevance in the textbook.

That being said, if you can afford the textbook it makes for a very good introductory reference, at the very least.

Assignments & Labs

ECSE 222 will have two types of assignments: shorter pen-and-paper take-home exercises, and longer technical lab sessions. The former are to be completed individually, and the latter in pre-determined groups of two. The goal of these assignments is to help you solidy the concepts we learn in class: I'm a firm believer in “learning by doing” and so these assignments will count as much as the exams do to your final score.

Given the two types of assignments, there will also be two types of tutorial sessions. During the first half of the course, the majority of the tutorial sessions will focus on discussing solutions to some of the pen-and-paper assignment questions. Afterwards, once you're more comfortable with the fundamental topics, lab tutorial sessions will begin in the latter half of the semester. You will be able to sign out an FPGA to work on lab problems at home, and the lab tutorial sessions themselves will be used to get you started on the lab problems and to evaluate your results.

All assignment tasks will have hard deadlines that are enforced to the second.

The specifications and supplementary material for the technical labs will be posted here throughout the semester. You are expected to read these before your lab session and, furthermore, we very much recommend you get a head start on the lab work using these specifications.

Late Policy & Extensions

The teaching staff and I will (of course) excuse absences for medical reasons, cultural and religious holidays, jury duty, and any other serious personal problems. When appropriate, these must be justified with valid documentation and presented to me and the Undergraduate Programs Administrator. Please refer to these guidelines for more information. Please note an important exception to this procedure in the case of modified circumstance surrounding final exams: according to Senate regulations, instructors are not permitted to make special arrangements for final exams. Please consult the Calendar, section 4.7.2.1, General University Information and Regulations at www.mcgill.ca. Special arrangements in emergencies may be requested at your Student Affairs Office.

In some of these exceptional circumstances, I may not be able to give an extension due to the nature of the assignments and tutorial sessions (i.e., assignment solutions may have been discussed during tutorials); when I can't, I will instead excuse you from the work item in question and adjust your final grade accordingly.

I encourage students who may require disability-related accommodations, as well as those experiencing mental or physical health challenges, to please advise the Office for Students with Disabilities (398-6009) as early in the term as possible so that we can provide appropriate accommodation to support your success.

Please note that, in accordance with article 15 of the Charter of Students' Rights, students may submit examination answers in either French or English. Additional policies governing academic issues which affect students can be found in the Handbook on Student Rights and Responsibilities.

Evaluation

The bottom line message regarding evaluation in this course is: if you put in a reasonable amount of time (see above: 2 to 4 hours per week outside of class/tutorials) into productive work, you will do very well. Unlike many core courses, your evaluation will be divided evenly between exams and assignments/labs:

Component Percentage
Pen-and-paper assignments (8 of these) 15% + 1% bonus
Pair Lab assignments 35% + 6% bonus
Midterm exam 25%
Final exam 25%

Each pen-and-paper assignment will be worth 2% of your final score (not including bonus points), and should only take you an hour or two to complete. I strongly recommend doing these in isolation: many of the midterm exam questions will be based on concepts that extend from the questions you see in these pen-and-paper assignments, so it's a good idea to be able to comfortably answer them. Similarly, the lab assignments will expose you to the hands-on aspects of digital hardware design using real-world CAD tools and hardware. Even though you'll work in pairs for these lab assignments, it's a good great idea to be fully aware of the methods and processes that led to your final lab solutions.

It's perfectly reasonable to take a bit of risk on these assignments: make mistakes and learn from your mistakes (this is, of course, how you'll have to approach problems in the Real WorldTM). That way, when the exams roll around, the hope is that you're better equipped to work on your own.

Pen & paper assignments should be submitted (physically) in the assignment drop-off bin on the 2nd floor of the Trottier building (next to the staircase) no later than 12:25pm EST on the Monday deadlines. Lab solutions will be submitted on myCourses, in the latter half of the semester.

Lecture Schedule & Content

Every week (with the exception of Thanksgiving), there will be three 50-minute lectures, and one two-hour tutorial/lab session. It's my understanding that you must register separately to the appropriate lecture, tutorial and lab sessions on Minerva!

  Monday Tuesday Wednesday Thursday Friday
Lecture
MDHAR G-10
12:35pm —
1:25pm
12:35pm —
1:25pm
12:35pm —
1:25pm
Tutorial & Lab
TR 2100 & 4180
3:35pm —
5:25pm
3:35pm —
5:25pm
3:35pm —
5:25pm
 

You can reach the TAs by e-mail or during their office hours.

Teaching Assistant E-mail Address
Hasan Mozafari sh.mozafari@mail.mcgill.ca
Sayantan Datta sayantan.datta@mail.mcgill.ca
Arash Ardakani arash.ardakani@mail.mcgill.ca
Alex Yin zixuan.yin@mail.mcgill.ca

I will hold additional “office” hours immediately after lectures, right outside the lecture hall: stick around after class to ask me questions. With the exception of scheduling meetings to view your midterm/final results, I will not take appointments during the semester; if you want to talk to me, right before or right after class is the best time.

I will design lectures to include plenty of time for questions and discussion. I will not field (non-administrative) questions regarding the assignents or labs, in class. The TAs will be available to answer these types of questions during the tutorials and/or during their office hours.

Below, I've included the full semester schedule. In general, I'd argue strongly that the best way to score well in this course (and with the smallest time commitment!) is to attend every lecture, take notes, work on the assignments independently, and ask questions. I will not be recording lectures, nor will I respond to e-mails during the semester: talking to me during one of the three weekly lectures is the best way to get a response.

All of the authorized course material will be posted on myCourses and cannot be redistributed without prior consent of the instructor. Unless where otherwise noted, all of the course material is Copyright © Derek Nowrouzezahrai (2016 — 2017). Students should be aware of the pitfalls stemming from potential inaccuracies present in third-party resources (e.g., YouTube, Wikipedia, etc.)

September 2017
MondayTuesdayWednesdayThursdayFriday
28 29 30 31 1  
4   5   6Introduction7   8Binary Numbers
11Binary Numbers12   13Boolean logic14   15Boolean logic
18Boolean logic19   20Introduction to VHDL21   22Combinational circuits
25Combinational circuits26   27Combinational circuits28   29Optimized implementation of combinational circuits

October 2017
MondayTuesdayWednesdayThursdayFriday
2Optimized implementation of combinational circuits3   4Optimized implementation of combinational circuits5   6Optimized implementation of combinational circuits
9Thanksgiving — NO CLASSES10   11Optimized implementation of combinational circuits12   13Combinational circuits
16Combinational circuits17   18Combinational circuits19   20Combinational circuits
23MIDTERM REVIEW24   25MIDTERM EXAM26   27Combinational circuit building blocks
30Combinational circuit building blocks31   1 2 3 

November 2017
MondayTuesdayWednesdayThursdayFriday
30 31 1Combinational circuit building blocks (review)2   3Combinational circuit building blocks
6Combinational circuit building blocks7   8Combinational circuit building blocks9   10Combinational circuit building blocks
13Combinational circuit building blocks14   15Combinational circuit building blocks16   17Combinational circuit building blocks
20Combinational circuit building blocks21   22Sequential circuits23   24Sequential circuits
27Sequential circuits28   29Synchronous sequential circuits30   1 

December 2017
MondayTuesdayWednesdayThursdayFriday
27 28 29 30 1Synchronous sequential circuits
4Synchronous sequential circuits5   6Synchronous sequential circuits7NO CLASS — Typo on Minerva!8  
11   12   13   14   15  
18   19   20   21   22  
25   26   27   28   29  
1 2 3 4 5 

Wednesday
6 Sep 2017
Introduction

  • Textbook: 1.1, 1.2, 1.3
  • Digital Hardware and the Design Process

Friday
8 Sep 2017
Binary Numbers

  • Textbook: 1.6
  • Why use binary?
  • Number representations

Monday
11 Sep 2017
Binary Numbers

  • Textbook: 2.1 − 2.5
  • Converting between different bases

Wednesday
13 Sep 2017
Boolean logic

  • Textbook: 2.1 − 2.5
  • Variables and Functions
  • Inversion and Truth Tables

Friday
15 Sep 2017
Boolean logic

  • Textbook: 2.1 − 2.5
  • Logic Gates and Networks
  • Boolean Algebra

Monday
18 Sep 2017
Boolean logic

  • Textbook: 2.1 − 2.5
  • Logic Gates and Networks
  • Boolean Algebra

Wednesday
20 Sep 2017
Introduction to VHDL

  • Textbook: 2.10

Friday
22 Sep 2017
Combinational circuits

  • Textbook: 2.6
  • Two-level circuits
    • Sum-of-Products and Product-of-Sums
      • synthesis using AND, OR, and NOT gates

Monday
25 Sep 2017
Combinational circuits

  • Textbook: 2.7
  • NAND and NOR Logic Networks

Wednesday
27 Sep 2017
Combinational circuits

  • Textbook: 2.8
  • Design Examples

Friday
29 Sep 2017
Optimized implementation of combinational circuits

  • Textbook 4.1
  • Karnaugh maps I

Monday
2 Oct 2017
Optimized implementation of combinational circuits

  • Textbook 4.1 − 4.4
  • Karnaugh maps II

Wednesday
4 Oct 2017
Optimized implementation of combinational circuits

  • Textbook 4.5
  • Karnaugh maps III

Friday
6 Oct 2017
Optimized implementation of combinational circuits

  • Textbook 4.5
  • Terminology
  • Formal minimization procedure
  • Karnaugh maps for POS

Wednesday
11 Oct 2017
Optimized implementation of combinational circuits

  • Textbook 4.5
  • Multiple-output synthesis

Friday
13 Oct 2017
Combinational circuits

  • Textbook 4.6
  • Multilevel synthesis I

Monday
16 Oct 2017
Combinational circuits

  • Textbook 4.6
  • Multilevel synthesis IIa

Wednesday
18 Oct 2017
Combinational circuits

  • Textbook 4.6
  • Multilevel synthesis IIb

Friday
20 Oct 2017
Combinational circuits

  • Textbook 4.6
  • Cubical representation and the tabular method

Monday
23 Oct 2017
MIDTERM REVIEW

Wednesday
25 Oct 2017
MIDTERM EXAM

Friday
27 Oct 2017
Combinational circuit building blocks

  • Textbook: 5.1, 5.1.1, 5.1.2, 5.3 (not including 5.3.3)
  • Number representations
  • Signed and unsigned integers
    • Negative numbers
    • Radix-Complement Schemes

Monday
30 Oct 2017
Combinational circuit building blocks

  • Textbook: 5.2
  • Arithmetic circuits
    • Addition of unsigned numbers
      • Decomposed Full-Adder

Wednesday
1 Nov 2017
Combinational circuit building blocks (review)

  • Textbook: 5.1, 5.1.1, 5.1.2, 5.3 (not including 5.3.3)
  • Signed and unsigned integers
    • Negative numbers
    • Radix-Complement Schemes
  • Addition of 1-bit unsigned numbers
    • Half-adder logic circuit

Friday
3 Nov 2017
Combinational circuit building blocks

  • Textbook: 5.2, 5.3.3, 5.4
  • Arithmetic circuits
    • Addition of unsigned numbers
      • Decomposed Full-Adder (review)
      • Ripple-Carry Adder
    • Addition and subtraction
    • Arithmetic overflow
    • Adder and subtractor units

Monday
6 Nov 2017
Combinational circuit building blocks

  • Textbook: 5.4
  • Arithmetic circuits
    • [optional] Addition of signed numbers
      • Carry-Lookahead Adder

Wednesday
8 Nov 2017
Combinational circuit building blocks

  • Arithmetic circuits
    • Textbook: 5.6
    • [optional] Multiplication of signed and unsigned integers

Friday
10 Nov 2017
Combinational circuit building blocks

  • Textbook: 6.1
  • Multiplexers (review)
    • wider MUXs
    • implementing logic functions with MUXs

Monday
13 Nov 2017
Combinational circuit building blocks

  • Textbook: 6.1
  • Multiplexers
    • implementing logic functions with MUXs
    • Shannon's expansion theorem

Wednesday
15 Nov 2017
Combinational circuit building blocks

  • Textbook: 6.2 − 6.5
  • Decoders
  • Encoders
  • [optional] Code Converters
  • [optional] Arithmetic Comparison Units

Friday
17 Nov 2017
Combinational circuit building blocks

  • Textbook: 4.12, 6.6
  • VHDL for Combinational Circuits

Monday
20 Nov 2017
Combinational circuit building blocks

  • Textbook: 4.12, 6.6
  • VHDL for Combinational Circuits

Wednesday
22 Nov 2017
Sequential circuits

  • Textbook: 7.1 − 7.3
  • Latches
    • Basic Latch
    • Gated SR Latch
    • Gated D Latch

Friday
24 Nov 2017
Sequential circuits

  • Textbook: 7.4 − 7.6
  • Memory
    • Flip-flops
      • Master-Slave and Edge-Triggered D Flip-Flops
        • T Flip-Flops
        • JK Flip-Flops

Monday
27 Nov 2017
Sequential circuits

  • Textbook: 7.8 − 7.9
  • Memory
    • Registers
    • Counters
      • Asynchronous Counters
      • Synchronous Counters
      • [optional; Textbook: 7.10, 7.11] Other types of counters: BCD, Ring, Johnson

Wednesday
29 Nov 2017
Synchronous sequential circuits

  • Textbook: 8.1 − 8.3
  • Finite-state machines
    • Basic Design Steps
      • Mealy State Model

Friday
1 Dec 2017
Synchronous sequential circuits

  • Textbook: 8.1 − 8.3
  • Finite-state machines
    • Basic Design Steps and State-assignment Problem
      • Mealy State Model

Monday
4 Dec 2017
Synchronous sequential circuits

  • Textbook: 8.4 − 8.6
  • Finite-state machines
    • Basic Design Steps and State-assignment Problem
      • Moore State Model
    • State minification

Wednesday
6 Dec 2017
Synchronous sequential circuits

  • Textbook: 8.4 − 8.7
  • Behavioral VHDL for FSMs
    • Serial Adder
      • Mealy- vs. Moore-type FSM for Serial Adder
    • Counter Design
      • State diagram and State table for a mod-8 counter

Thursday
7 Dec 2017
NO CLASS — Typo on Minerva!

Ethics

Plagiarism is an academic offense of misrepresenting authorship that can result in penalties up to expulsion for an undergraduate. It is dishonorable but not illegal. Note that it is possible to plagiarise your own work, for example, by resubmitting work from another course without attribution.

Copyright violation is an independent concept based on the legal right to use material, which is enforced by civil courts.

McGill University values academic integrity. Therefore, all students must understand the meaning and consequences of cheating, plagiarism and other academic offences under the Code of Student Conduct and Disciplinary Procedures. See www.mcgill.ca/integrity for more information, as well as www.mcgill.ca/students/srr/honest with respect to student rights and responsibilities.

Course website and assignments formatted using Markdeep 0.16  
and Copyright © Derek Nowrouzezahrai (2016 - 2017)