For all administrative/registration issues, please do *not* contact the course staff: instead, contact the [McGill ECE Undergraduate Programs Administrator](http://www.mcgill.ca/ece/facultystaff/under). I will not reply to any e-mails pertaining to administrative issues or to information provided during lectures.

Requirements
======================================================================================
Prerequisites
: - [*ECSE 202*: Introduction to Software Development](http://www.mcgill.ca/study/2016-2017/courses/ecse-202)
Textbook (on reserve at the library and available at the McGill Bookstore)
: - _Brown and Vranesic_, Digital Logic with VHDL Design, *3rd Ed*, McGraw-Hill.
Equipment
: ![Altera DE1-SoC: 222's official _hammer_.](http://www.emb4fun.de/fpga/de1socghrd/images/de1soc.jpg width="30%" border="2")
You will **be responsible for** signing out (and returning, _on time_!) an Altera DE1-SoC FPGA board for use when developing and testing your lab assignments. You will be able to do some of the design and simulation work outside of the actual lab sessions, using software that you can install on your own laptops/desktops. During the 2-hour lab sessions, lab time will be used to demonstrate your lab experiments to the TAs for evaluation.
**Time**
I **strongly recommend** attending lectures: you'll save more time (and hopefully gain a better understanding) following the instructor _face-to-face_ through the course slides, compared to exclusively and independently reading the slides (and/or the textbook).
Plan to invest an average of *2 to 4 hours per week* on this course, in addition to the (almost) 3 hours of lecture and 2 hours of tutorials/labs. The balance will shift from (possibly) fewer hours spent on pen-and-paper assignments early in the semester, to (possibly) longer hours spent working on the labs later in the semester.
It's a good idea to get in the habit of spending the time necessary to _understand_ the course topics, in part through an independent completion of the pen-and-paper assignments, early on in the semester. In the latter-half of the course, when labs begin, the pace of the course will accelerate significantly. Here, it's essential that you communicate effectively with your lab partner: I recommend a "work to understand stuff together" approach, rather than a "divide-and-conquer" approach, for the labs.
All that being said, it's should be clear that you have complete freedom in how you choose to spend your time: there may very well be many valid paths to success in ECSE 222, and the ones I outlined above are motivated simply by the habits I've observed from successful students over the years.
Participation
: ![Don't be shy: speak up in class.](https://magingalagadngsining.files.wordpress.com/2014/09/participate-in-class.jpg width="30%" border="2")
ECSE 222 is a mandatory course in the ECSE curriculum, which means we're going to have large classes. I _love_ teaching to large classes, and I'm going to call on you to help foster a genuine environment of investigation during the semester. Many of the lectures will include example problems that we'll solve *together* in class. The operative word here, "together", means that I'm not just going to walk you through solutions... it means that we're going to stumble through solutions together, through discussion.
Now's not the time to be shy! When in class: ask questions, take risks (you're not being graded on what you say in class!), don't be afraid to give a wrong answer... often, it's the wrong answers that spark the most interesting discussions.
Readings
=================================================================================
My course slides and lectures will be based very closely on the textbook for the course, _Brown and Vranesic_'s *Digital Logic with VHDL Design* (3rd edition, McGraw-Hill). The course schedule below makes reference to relevant textbook sections for each lecture, *however*, if you pay attention and participate during class, the textbook readings can serve primarily as supplemental instruction: it's always handy to hear someone _different_ (in this case, Brown and Vranesic) explain the _same ideas_ that I will cover in the class, but there won't be additional information of relevance in the textbook.
That being said, if you can afford the textbook it makes for a very good introductory reference, at the very least.
Assignments & Labs
------------------------------------------------------------
ECSE 222 will have two types of assignments: shorter pen-and-paper take-home exercises, and longer technical lab sessions. The goal of these assignments is to help you solidy the concepts we learn in class: I'm a firm believer in _"learning by doing"_ and so these assignments will count about as much as the exams do to your final score.
Given the two types of assignments, there will also be two types of tutorial sessions. During the first half of the course, the majority of the tutorial sessions will focus on _discussing_ solutions to some of the pen-and-paper assignment questions. Afterwards, once you're more comfortable with the fundamental topics, lab tutorial sessions will begin in the latter half of the semester. You will be able to sign out an FPGA to work on lab problems at home, and the lab tutorial sessions themselves will be used to get you started on the lab problems and to evaluate your results.
All assignment tasks will have hard deadlines that are enforced to the second.
The specifications and supplementary material for the technical labs will be posted here throughout the semester. You are expected to read these before your lab session and, furthermore, we very much recommend you get a head start on the lab work using these specifications.
- Click [here](http://www.cim.mcgill.ca/~derek/ecse222lab/Lab1/) to access the **Lab 1 Specifications**
- Click [here](http://www.cim.mcgill.ca/~derek/ecse222lab/Lab2/) to access the **Lab 2 Specifications**
- Click [here](http://www.cim.mcgill.ca/~derek/ecse222lab/Lab3/) to access the **Lab 3 Specifications**
- Click [here](http://www.cim.mcgill.ca/~derek/ecse222lab/Lab4/) to access the **Lab 4 Specifications**
Late Policy & Extensions
------------------------------------------------------------
The teaching staff and I will (of course) excuse absences for medical reasons, cultural and religious holidays, jury duty, and any other serious personal problems. When appropriate, these must be justified with valid documentation and presented to me and the [Undergraduate Programs Administrator](prema.menon@mcgill.ca). Please refer to [these guidelines](http://www.mcgill.ca/engineering/current-students/undergraduate/courses-registration/exams-assessment/midterms-and-class-tests) for more information. Please note an important exception to this procedure in the case of modified circumstance surrounding final exams: according to Senate regulations, instructors are not permitted to make special arrangements for final exams. Please consult the Calendar, section 4.7.2.1, General University Information and Regulations at www.mcgill.ca. Special arrangements in emergencies may be requested at your Student Affairs Office.
In some of these exceptional circumstances, I may not be able to give an extension due to the nature of the assignments and tutorial sessions (i.e., assignment solutions may have been discussed during tutorials); when I can't, I will instead excuse you from the work item in question and adjust your final grade accordingly.
I encourage students who may require disability-related accommodations, as well as those experiencing mental or physical health challenges, to please advise the [Office for Students with Disabilities](https://www.mcgill.ca/osd/office-students-disabilities) (398-6009) as early in the term as possible so that we can provide appropriate accommodation to support your success.
Please note that, in accordance with _article 15_ of the *Charter of Students' Rights*, students may submit examination answers in either French or English. Additional policies governing academic issues which affect students can be found in the Handbook on Student Rights and Responsibilities.
Evaluation
=====================================================================
The bottom line message regarding evaluation in this course is: if you put in a _reasonable_ amount of time (see above: 2 to 4 hours per week outside of class/tutorials) into _productive_ work, you will do very well. Unlike many core courses, your evaluation will be divided *evenly* between exams and assignments/labs:
Component | Percentage
-----------------------------------------------------|-------------------
Pen-and-paper assignments (6 + 1 of these) | 12 + 3% + up to 2% more bonus
Lab assignments | 35%
Midterm exam | 25%
Final exam | 25%
Each pen-and-paper assignment will be worth 2% of your final score (_not including bonus points_), and should only take you an hour or two to complete. I strongly recommend doing these _in isolation_: many of the midterm exam questions will be based on concepts that extend from the questions you see in these pen-and-paper assignments, so it's a good idea to be able to comfortably answer them. Similarly, the lab assignments will expose you to the hands-on aspects of digital hardware design using real-world CAD tools and hardware. Even though you'll work in pairs for these lab assignments, it's a ~~good~~ great idea to be fully aware of the methods and processes that led to your final lab solutions.
It's perfectly reasonable to take a bit of risk on these assignments: make mistakes and _learn_ from your mistakes (this is, of course, how you'll have to approach problems in the Real World*
Pen & paper assignments should be submitted (physically) in the assignment drop-off bin on the 2nd floor of the Trottier building (next to the staircase) __no later than 12:25pm EST on the Monday deadlines__. Lab solutions will be submitted on myCourses, in the latter half of the semester.

Lecture Schedule & Content
=====================================================================
Every week (with the exception of Thanksgiving), there will be three 50-minute lectures, and one two-hour tutorial/lab session. It's my understanding that you must register separately to the appropriate lecture, tutorial and lab sessions on Minerva!
|Monday | Tuesday | Wednesday | Thursday | Friday
--------------------------------------------------------------------|---------------|-------------|--------------|-------------|------------------------------
*Lecture**LEA 232* |9:35pm --

10:25pm | |9:35pm --

10:25pm | |9:35pm --

10:25pm *Tutorial & Lab*

*TR 0060 & 4060*|1:35pm --

3:25pm |1:35pm --

3:25pm| 1:35pm --

3:25pm |1:35pm --

3:25pm| 1:35pm --

3:25pm You can reach the TAs by e-mail or during tutorial hours. Teaching Assistant | E-mail Address ----------------------------------|--------------------------------- Arash Ardakani | arash.ardakani@mail.mcgill.ca Alex Yin | zixuan.yin@mail.mcgill.ca I will hold additional office hours immediately after lectures, right outside the lecture hall: stick around after class to ask me questions. Otherwise, you will have to arrange a face-to-face meeting with me by verbal request (i.e., in class, not by e-mail) and with an appropriate agenda. I will design lectures to include plenty of time for questions and discussion. I will __not__ field (non-administrative) questions regarding the assignents or labs, in class. The TAs will be available to answer these types of questions during the tutorials and/or during their office hours. Below, I've included the full semester schedule. In general, I'd argue strongly that the best way to score well in this course (and with the smallest time commitment!) is to **attend every lecture**, **take notes**, **work on the assignments independently**, and **ask questions**. I will __not__ be recording lectures, __nor__ will I respond to e-mails during the semester: talking to me during one of the three weekly lectures is the best way to get a response.

All of the authorized course material will be posted on myCourses and _cannot be redistributed without prior consent of the instructor_. Unless where otherwise noted, all of the course material is __Copyright © Derek Nowrouzezahrai (2016 -- 2018)__. Students should be aware of the pitfalls stemming from potential inaccuracies present in third-party resources (e.g., YouTube, Wikipedia, etc.)

Wednesday September 5, 2018: Introduction
- _Textbook: 1.1, 1.2, 1.3_
- Digital Hardware and the Design Process
Friday September 7, 2018: Binary Numbers
- _Textbook: 1.6_
- Why use binary?
- Number representations
Monday September 10, 2018: Binary Numbers
- _Textbook: 2.1 - 2.5_
- Converting between different bases
Wednesday September 12, 2018: Boolean logic
- _Textbook: 2.1 - 2.5_
- Variables and Functions
- Inversion and Truth Tables
Friday September 14, 2018: Boolean logic
- _Textbook: 2.1 - 2.5_
- Logic Gates and Networks
- Boolean Algebra
Monday September 17, 2018: Boolean logic
- _Textbook: 2.1 - 2.5_
- Logic Gates and Networks
- Boolean Algebra
Wednesday September 19, 2018: Introduction to VHDL
- _Textbook: 2.10_
Friday September 21, 2018: Combinational circuits
- _Textbook: 2.6_
- Two-level circuits
- Sum-of-Products and Product-of-Sums
- synthesis using AND, OR, and NOT gates
Monday September 24, 2018: Combinational circuits
- _Textbook: 2.7_
- NAND and NOR Logic Networks
Wednesday September 26, 2018: Combinational circuits
- _Textbook: 2.8_
- Design Examples
Friday September 28, 2018: Optimized implementation of combinational circuits
- _Textbook 4.1_
- Karnaugh maps I
Monday October 1, 2018: Optimized implementation of combinational circuits
- _Textbook 4.1 - 4.4_
- Karnaugh maps II
Wednesday October 3, 2018: Optimized implementation of combinational circuits
- _Textbook 4.5_
- Karnaugh maps III
Friday October 5, 2018: Optimized implementation of combinational circuits
- _Textbook 4.5_
- Terminology
- Formal minimization procedure
- Karnaugh maps for POS
(Monday October 8, 2018): Thanksgiving -- NO CLASSES
Wednesday October 10, 2018: Optimized implementation of combinational circuits
- _Textbook 4.5_
- Multiple-output synthesis
Friday October 12, 2018: Combinational circuits
- _Textbook 4.6_
- Multilevel synthesis I
Monday October 15, 2018: Combinational circuits
- _Textbook 4.6_
- Multilevel synthesis I
Wednesday October 17, 2018: Combinational circuits
- _Textbook 4.6_
- Multilevel synthesis IIa
Friday October 19, 2018: Combinational circuits
- _Textbook 4.6_
- Multilevel synthesis IIb
Monday October 22, 2018: MIDTERM REVIEW
Wednesday October 24, 2018: **MIDTERM EXAM**
Friday October 26, 2018: Combinational circuit building blocks
- _Textbook: 5.1, 5.1.1, 5.1.2, 5.3 (not including 5.3.3)_
- Number representations
- Signed and unsigned integers
- Negative numbers
- Radix-Complement Schemes
Monday October 29, 2018: Combinational circuit building blocks
- _Textbook: 5.2_
- Arithmetic circuits
- Addition of unsigned numbers
- Decomposed Full-Adder
Wednesday October 31, 2018: Combinational circuit building blocks (review)
- _Textbook: 5.1, 5.1.1, 5.1.2, 5.3 (not including 5.3.3)_
- Signed and unsigned integers
- Negative numbers
- Radix-Complement Schemes
- Addition of 1-bit unsigned numbers
- Half-adder logic circuit
Friday November 2, 2018: Combinational circuit building blocks
- _Textbook: 5.2, 5.3.3, 5.4_
- Arithmetic circuits
- Addition of unsigned numbers
- Decomposed Full-Adder (review)
- Ripple-Carry Adder
- Addition and subtraction
- Arithmetic overflow
- Adder and subtractor units
Monday November 5, 2018: Combinational circuit building blocks
- _Textbook: 5.4_
- Arithmetic circuits
- [optional] Addition of signed numbers
- Carry-Lookahead Adder
Wednesday November 7, 2018: Combinational circuit building blocks
- Arithmetic circuits
- _Textbook: 5.6_
- [optional] Multiplication of signed and unsigned integers
Friday November 9, 2018: Combinational circuit building blocks
- _Textbook: 6.1_
- Multiplexers (review)
- wider MUXs
- implementing logic functions with MUXs
Monday November 12, 2018: Combinational circuit building blocks
- _Textbook: 6.1_
- Multiplexers
- implementing logic functions with MUXs
- Shannon's expansion theorem
Wednesday November 14, 2018: Combinational circuit building blocks
- _Textbook: 6.2 - 6.5_
- Decoders
- Encoders
- [optional] Code Converters
- [optional] Arithmetic Comparison Units
Friday November 16, 2018: Combinational circuit building blocks
- _Textbook: 4.12, 6.6_
- VHDL for Combinational Circuits
Monday November 19, 2018: Combinational circuit building blocks
- _Textbook: 4.12, 6.6_
- VHDL for Combinational Circuits
Wednesday November 21, 2018: Sequential circuits
- _Textbook: 7.1 - 7.3_
- Latches
- Basic Latch
- Gated SR Latch
- Gated D Latch
Friday November 23, 2018: Sequential circuits
- _Textbook: 7.4 - 7.6_
- Memory
- Flip-flops
- Master-Slave and Edge-Triggered D Flip-Flops
- T Flip-Flops
- JK Flip-Flops
Monday November 26, 2018: Sequential circuits
- _Textbook: 7.8 - 7.9_
- Memory
- Registers
- Counters
- Asynchronous Counters
- Synchronous Counters
- [optional; _Textbook: 7.10, 7.11_] Other types of counters: BCD, Ring, Johnson
Wednesday November 28, 2018: Synchronous sequential circuits
- _Textbook: 8.1 - 8.3_
- Finite-state machines
- Basic Design Steps
- Mealy State Model
Friday November 30, 2018: Synchronous sequential circuits
- _Textbook: 8.1 - 8.3_
- Finite-state machines
- Basic Design Steps and State-assignment Problem
- Mealy State Model
Monday December 3, 2018: Synchronous sequential circuits
- _Textbook: 8.4 - 8.6_
- Finite-state machines
- Basic Design Steps and State-assignment Problem
- Moore State Model
- State minification
Tuesday December 4, 2018: Synchronous sequential circuits
- _Textbook: 8.4 - 8.7_
- Behavioral VHDL for FSMs
- Serial Adder
- Mealy- vs. Moore-type FSM for Serial Adder
- Counter Design
- State diagram and State table for a mod-8 counter
Ethics
=====================================================================
*Plagiarism* is an academic offense of misrepresenting authorship that can result in penalties up to expulsion for an undergraduate. It is dishonorable but not illegal. Note that it is possible to plagiarise _your own work_, for example, by resubmitting work from another course without attribution.
*Copyright* violation is an independent concept based on the legal right to use material, which is enforced by civil courts.
McGill University values academic integrity. Therefore, all students must understand the meaning and consequences of cheating, plagiarism and other academic offences under the *Code of Student Conduct and Disciplinary Procedures*. See [www.mcgill.ca/integrity](www.mcgill.ca/integrity) for more information, as well as [www.mcgill.ca/students/srr/honest](www.mcgill.ca/students/srr/honest) with respect to student rights and responsibilities.