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* | For all administrative/registration issues, please do *not* contact the course | *
* | staff: instead, contact the McGill ECE Undergraduate Programs Administrator. | *
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Requirements
======================================================================================
Prerequisites
: - [*ECSE 202*: Introduction to Software Development](http://www.mcgill.ca/study/2016-2017/courses/ecse-202)
Textbook (on reserve at the library and available at the McGill Bookstore)
: - _Brown and Vranesic_, Digital Logic with VHDL Design, *3rd Ed*, McGraw-Hill.
Equipment
: ![Altera DE1-SoC: 222's official _hammer_.](http://www.emb4fun.de/fpga/de1socghrd/images/de1soc.jpg width="30%" border="2")
Each lab team will be able to sign out an Altera DE1-SoC FPGA board for use when developing and testing your lab assignments. You will be able to do much of the design and simulation work outside of the actual lab sessions, using software that you can install on your own laptops/desktops. During the 2-hour lab sessions, lab time will be used to demonstrate the lab experiments to your TAs for evaluation.
Time
: ![Putting pen to paper: do this FTW.](http://internetnotes.in/wp-content/uploads/2016/10/IMG_9994.jpg width="30%" border="2")
I _strongly recommend_ attending lectures: you'll save more time (and hopefully gain a better understanding) following me _face-to-face_ through my course slides, compared to reading my slides (and/or the textbook) on your own.
Plan to invest an average of *2 to 4 hours per week* on this course, in addition to the (almost) 3 hours of lecture and 2 hours of tutorials/labs. The balance will shift from (possibly) fewer hours spent on pen-and-paper assignments early in the semester, to (possibly) longer hours spent working on the labs later in the semester.
It's a good idea to get in the habit of spending the time necessary to _understand_ the course topics, in part through the (individual) completion of the pen-and-paper assignments, early on in the semester. In the latter-half of the course, when labs begin, it's essential that you communicate effectively with your lab partner: I recommend a "work to understand stuff together" approach, rather than a "divide-and-conquer" approach, for the labs.
All that being said, it's should be clear that you have complete freedom in how you choose to spend your time: there may very well be many valid paths to success in ECSE 222, and the ones I outlined above are simply the paths I feel you should consider taking.
Participation
: ![Don't be shy: speak up in class.](https://magingalagadngsining.files.wordpress.com/2014/09/participate-in-class.jpg width="30%" border="2")
ECSE 222 is a mandatory course in the ECSE curriculum, which means we're going to have large classes. I _love_ teaching to large classes, and I'm going to call on you to help foster a genuine environment of investigation during the semester. Many of the lectures will include example problems that we'll solve *together* in class. The operative word here, "together", means that I'm not going to walk you through solutions... it means that we're going to stumble through solutions together, through discussion.
Now's not the time to be shy! When in class: ask questions, take risks (you're not being graded on what you say in class!), don't be afraid to give a wrong answer... often, it's the wrong answers that spark the most interesting discussions.
Readings
=================================================================================
My course slides and lectures will be based very closely on the textbook for the course, _Brown and Vranesic_'s *Digital Logic with VHDL Design* (3rd edition, McGraw-Hill). The course schedule below makes reference to relevant textbooks sections for each lecture, *however*, if you pay attention and participate during class, the textbook readings may only serve as supplemental information: it's always handy to hear someone _different_ (in this case, Brown and Vranesic) explain the _same ideas_ that I will cover in the class, but there shouldn't be any additional information of relevance in the textbook.
That being said, if you can afford the textbook it makes for a very good introductory reference, at the very least.
Assignments & Labs
------------------------------------------------------------
ECSE 222 will have two types of assignments: shorter pen-and-paper take-home exercises, and longer technical lab sessions. The former are to be completed individually, and the latter in pairs (of two, typically). The goal of these assignments is to help you solidy the concepts we learn in class: I'm a firm believer in _"learning by doing"_ and so these assignments will count as much as the exams do to your final score.
Given the two types of assignments, there will also be two types of tutorial sessions. During the first part of the course, the majority of the tutorial sessions will focus on _discussing_ solutions to some of the pen-and-paper assignment questions (and possibly other problem sets). Afterwards, once you're more comfortable with the fundamental topics, lab tutorial sessions will begin in the latter half of the semester. You will be able to sign out an FPGA to work on lab problems at home, and the lab tutorial sessions themselves will be used to get you started on the lab problems and to evaluate your results.
All assignment tasks will have hard deadlines that are enforced to the second.
The specifications and supplementary material for the technical labs will be posted here throughout the semester. You are expected to read these before your lab session and, furthermore, we highly recommend you get a head start on the lab work using these specifications.
- Click [here](http://www.cim.mcgill.ca/~derek/ecse222lab/Lab1/) to access the **Lab 1 Specifications**
- Click [here](http://www.cim.mcgill.ca/~derek/ecse222lab/Lab2/) to access the **Lab 2 Specifications**
- Click [here](http://www.cim.mcgill.ca/~derek/ecse222lab/Lab3/) to access the **Lab 3 Specifications**
- Click [here](http://www.cim.mcgill.ca/~derek/ecse222lab/Lab4/) to access the **Lab 4 Specifications**
Late Policy & Extensions
------------------------------------------------------------
The teaching staff and I will (of course) excuse absences for medical reasons, cultural and religious holidays, jury
duty, and serious personal problems. When appropriate, these must be justified with valid documentation and presented to me and the [Undergraduate Programs Administrator](prema.menon@mcgill.ca). Please refer to [these guidelines](http://www.mcgill.ca/engineering/current-students/undergraduate/courses-registration/exams-assessment/midterms-and-class-tests) for more information. Please note an important exception to this procedure in the case of modified circumstance surrounding final exams: according to Senate regulations, instructors are not permitted to make special arrangements for final exams. Please consult the Calendar, section 4.7.2.1, General University Information and Regulations at www.mcgill.ca. Special arrangements in emergencies may be requested at your Student Affairs Office.
In some of these exceptional circumstances, I may not be able to give an extension due to the nature of the assignments and tutorial sessions (i.e., assignment solutions may be discussed during tutorials); when I can't, I will instead excuse you from the work item in question and adjust your final grade accordingly.
I encourage students who may require disability-related accommodations, as well as those experiencing mental or physical health challenges, to please advise the [Office for Students with Disabilities](https://www.mcgill.ca/osd/office-students-disabilities) (398-6009) as early in the term as possible so that we can provide appropriate accommodation to support your success.
Please note that, in accordance with _article 15_ of the *Charter of Students' Rights*, students may submit examination answers in either French or English. Additional policies governing academic issues which affect students can be found in the Handbook on Student Rights and Responsibilities.
Evaluation
=====================================================================
The bottom line message regarding evaluation in this course is: if you put in a _reasonable_ amount of time (see above: 2 to 4 hours per week outside of class/tutorials) into _productive_ work, you will do very well. Unlike many core courses, your evaluation will be divided evenly between exams and assignments/labs:
Component | Percentage
-----------------------------------------------------|-------------------
Pen-and-paper assignments (about 7 of these) | 15% *+ $\geq$ 1% bonus*
*Pair* Lab assignments | 35%
Midterm exam | 25%
Final exam | 25%
Each pen-and-paper assignment will be worth roughly 2% of your final score, and should only take you an hour or two to complete. I strongly recommend doing these _in isolation_/individually: many of the midterm exam questions will be on par with those you see in these pen-and-paper assignments, so it's a good idea to really hammer home the concepts here. Similarly, the lab assignments will expose you to the hands-on aspects of digital hardware design using real-world CAD tools and hardware. Even though you'll work in pairs for these lab assignments, it's a ~~good~~ great idea to be fully aware of the methods and processes that led to your final lab solutions. I'd be lying if I said that ideas from the lab component of the course will not be appearing on the final exam.
It's perfectly reasonable to take a bit of risk on these assignments: make mistakes and _learn_ from your mistakes (this is what you'll have to do anyways, in the Real World*
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* | Pen & paper assignments should be submitted (physically) in the assignment drop- | *
* | off bin on the 2nd floor of the Trottier building (next to the staircase) no | *
* | later than 10:25am EST on the Monday deadlines. Lab solutions will be submitted | *
* | on myCourses, in the latter portion of the semester. | *
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Lecture Schedule & Content
=====================================================================
Every week (with the exception of reading week), there will be three 50-minute lectures, and one two-hour tutorial session. It's my understanding that you must register separately to the appropriate lecture, tutorial and lab sessions on Minerva!
Monday | Wednesday | Friday
------------------------------------------------|------------------------------------------------|---------------------------------------
*Lecture*: 10:35am - 11:25am (MC 204) |*Lecture*: 10:35am - 11:25am (MC 204) |*Lecture*: 10:35am - 11:25am (MC 204)
*Tutorial/Lab A*: 3:35pm - 5:25pm (TR 60 & 4180)|*Tutorial/Lab B*: 3:35pm - 5:25pm (TR 60 & 4180)|*Tutorial/Lab C*: 3:35pm - 5:25pm (TR 60 & 4180)
TAs will announce their office hours during the first week of tutorials.
Teaching Assistant | E-mail Address
----------------------------------|---------------------------------
Shabbir Hussain | shabbir.hussain@mail.mcgill.ca
Loren Lugosch | loren.lugosch@gmail.com
Hasan Mozafari | sh.mozafari@mail.mcgill.ca
I will not hold additional office hours outside of the lectures: I will design lectures to include plenty of time for questions and discussion. I will not field (non-administrative) questions regarding the assignents or labs, in class. The TAs will be available to answer these types of questions during the tutorials and during their office hours.
Below I've inlucded the full (albeit tentative, depending on our pace) semester schedule. Some _optional_, non-essential topics (for this course) are included in the schedule, and we may or may not get around to covering them during the semester. These topics will be covered later on in your undergraduate curriculum, but if we do get around to them, I'll try to give you a bit of a unique perspective to supplement what you'll study in the future.
Wednesday Jan 4, 2017: Introduction
- _Textbook: 1.1, 1.2, 1.3_
- Digital Hardware and the Design Process
Friday Jan 6, 2017: Binary Numbers
- _Textbook: 1.6_
- Why use binary?
- Number representations
Monday Jan 9, 2017: Binary Numbers
- _Textbook: 2.1 - 2.5_
- Converting between different bases
Wednesday Jan 11, 2017: Boolean logic
- _Textbook: 2.1 - 2.5_
- Variables and Functions
- Inversion and Truth Tables
Friday Jan 13, 2017: Boolean logic
- _Textbook: 2.1 - 2.5_
- Logic Gates and Networks
- Boolean Algebra
Monday Jan 16, 2017: Boolean logic
- _Textbook: 2.1 - 2.5_
- Logic Gates and Networks
- Boolean Algebra
Wednesday Jan 18, 2017: Introduction to VHDL
- _Textbook: 2.10_
Friday Jan 20, 2017: Combinational circuits
- _Textbook: 2.6_
- Two-level circuits
- Sum-of-Products and Product-of-Sums
- synthesis using AND, OR, and NOT gates
Monday Jan 23, 2017: Combinational circuits
- _Textbook: 2.7_
- NAND and NOR Logic Networks
Wednesday Jan 25, 2017: Combinational circuits
- _Textbook: 2.8_
- Design Examples
Friday Jan 27, 2017: Optimized implementation of combinational circuits
- _Textbook 4.1_
- Karnaugh maps I
Monday Jan 30, 2017: Optimized implementation of combinational circuits
- _Textbook 4.1 - 4.4_
- Karnaugh maps II
Wednesday Feb 1, 2017: Optimized implementation of combinational circuits
- _Textbook 4.5_
- Karnaugh maps III
Friday Feb 3, 2017: Optimized implementation of combinational circuits
- _Textbook 4.5_
- Terminology
- Formal minimization procedure
- Karnaugh maps for POS
Monday Feb 6, 2017: Optimized implementation of combinational circuits
- _Textbook 4.5_
- Multiple-output synthesis
Wednesday Feb 8, 2017: Combinational circuits
- _Textbook 4.6_
- Multilevel synthesis I
Friday Feb 10, 2017: Combinational circuits
- _Textbook 4.6_
- Multilevel synthesis II
Monday Feb 13, 2017: Combinational circuits
- _Textbook 4.6_
- Cubical representation and the tabular method
Wednesday Feb 15, 2017: Combinational circuits
- _Textbook 4.6_
- Cubical representation and the tabular method
Friday Feb 17, 2017: MIDTERM REVIEW
Monday Feb 20, 2017: **MIDTERM EXAM**
Wednesday Feb 22, 2017: Combinational circuit building blocks
- _Textbook: 5.1, 5.1.1, 5.1.2, 5.3 (not including 5.3.3)_
- Number representations
- Signed and unsigned integers
- Negative numbers
- Radix-Complement Schemes
Friday Feb 24, 2017: Combinational circuit building blocks
- _Textbook: 5.2_
- Arithmetic circuits
- Addition of unsigned numbers
- Decomposed Full-Adder
(Monday Feb 27, 2017): Reading Week
(Wednesday Mar 1, 2017): Reading Week
(Friday Mar 3, 2017): Reading Week
Monday Mar 6, 2017: Combinational circuit building blocks (review)
- _Textbook: 5.1, 5.1.1, 5.1.2, 5.3 (not including 5.3.3)_
- Signed and unsigned integers
- Negative numbers
- Radix-Complement Schemes
- Addition of 1-bit unsigned numbers
- Half-adder logic circuit
Wednesday Mar 8, 2017: Combinational circuit building blocks
- _Textbook: 5.2, 5.3.3, 5.4_
- Arithmetic circuits
- Addition of unsigned numbers
- Decomposed Full-Adder (review)
- Ripple-Carry Adder
- Addition and subtraction
- Arithmetic overflow
- Adder and subtractor units
Friday Mar 10, 2017: Combinational circuit building blocks
- _Textbook: 6.1_
- Multiplexers (review)
- wider MUXs
- implementing logic functions with MUXs
Monday Mar 13, 2017: Combinational circuit building blocks
- _Textbook: 6.1_
- Multiplexers
- implementing logic functions with MUXs
- Shannon's expansion theorem
(Wednesday Mar 15, 2017): Classes cancelled
Friday Mar 17, 2017: Combinational circuit building blocks
- _Textbook: 6.2 - 6.5_
- Decoders
- Encoders
- [optional] Code Converters
- [optional] Arithmetic Comparison Units
Monday Mar 20, 2017: Combinational circuit building blocks
- _Textbook: 4.12, 6.6_
- VHDL for Combinational Circuits
Wednesday Mar 22, 2017: Combinational circuit building blocks
- _Textbook: 4.12, 6.6_
- VHDL for Combinational Circuits
Friday Mar 24, 2017: Sequential circuits
- _Textbook: 7.1 - 7.3_
- Latches
- Basic Latch
- Gated SR Latch
- Gated D Latch
Monday Mar 27, 2017: Sequential circuits
- _Textbook: 7.4 - 7.6_
- Memory
- Flip-flops
- Master-Slave and Edge-Triggered D Flip-Flops
- T Flip-Flops
- JK Flip-Flops
Wednesday Mar 29, 2017: Sequential circuits
- _Textbook: 7.8 - 7.9_
- Memory
- Registers
- Counters
- Asynchronous Counters
- Synchronous Counters
- [optional; _Textbook: 7.10, 7.11_] Other types of counters: BCD, Ring, Johnson
Friday Mar 31, 2017: Synchronous sequential circuits
- _Textbook: 8.1 - 8.3_
- Finite-state machines
- Basic Design Steps
- Mealy State Model
Monday Apr 3, 2017: Synchronous sequential circuits
- _Textbook: 8.1 - 8.3_
- Finite-state machines
- Basic Design Steps and State-assignment Problem
- Mealy State Model
Wednesday Apr 5, 2017: Synchronous sequential circuits
- _Textbook: 8.4 - 8.6_
- Finite-state machines
- Basic Design Steps and State-assignment Problem
- Moore State Model
- State minification
Friday Apr 7, 2017: Synchronous sequential circuits
- _Textbook: 8.4 - 8.7_
- Behavioral VHDL for FSMs
- Serial Adder
- Mealy- vs. Moore-type FSM for Serial Adder
- Counter Design
- State diagram and State table for a mod-8 counter
Monday Apr 10, 2017: FINAL EXAM REVIEW
Ethics
=====================================================================
*Plagiarism* is an academic offense of misrepresenting authorship that can result in penalties up to expulsion for an undergraduate. It is dishonorable but not illegal. Note that it is possible to plagiarise _your own work_, for example, by resubmitting work from another course without attribution.
*Copyright* violation is an independent concept based on the legal right to use material, which is enforced by civil courts.
McGill University values academic integrity. Therefore, all students must understand the meaning and consequences of cheating, plagiarism and other academic offences under the *Code of Student Conduct and Disciplinary Procedures*. See [www.mcgill.ca/integrity](www.mcgill.ca/integrity) for more information, as well as [www.mcgill.ca/students/srr/honest](www.mcgill.ca/students/srr/honest) with respect to student rights and responsibilities.