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A Floating-Point Convolution Processor

The project involves the design and implementation of a specialized processor board for a workstation. The processor can perform two dimensional convolution on an image array of programmable size using double-precision floating point operands. A systolic array architecture was selected. The interface implementation incorporates a Direct Memory Access controller to the VME bus.

J.F. Panisset, A.S. Malowany

Thierry Baron
Mon Nov 13 10:43:02 EST 1995