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Fabricating and Testing a VLSI Systolic Convolution Cell for Image Processing

Authors: [tex2html_wrap4238]A. Botzas, A.S. Malowany

Investigator username: malowany

Category: perception

Subcategory: sensor and processor design

The two-dimensional discrete convolution operator is targeted for performance improvement in order to speed up image processing tasks. Systolic arrays were selected for parallel processing of the convolution problem. The VLSI systolic cell uses three pipelined stages to process each set of operands in 16 clock cycles. The tested performance of the fabricated chip is 80 MFLOPS.